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An optimized tag sorting circuit in WFQ scheduler based on leading zero counting
文献类型:会议
作者:Huang, Xiao-Ping[1]  Fan, Xiao-Ya[2]  Zhang, Sheng-Bing[3]  Zhang, Fan[4]  
机构:[1]Computer School, Northwestern Polytechnical University, Xian 710072, China
[2]Computer School, Northwestern Polytechnical University, Xian 710072, China
[3]Computer School, Northwestern Polytechnical University, Xian 710072, China
[4]Computer School, Northwestern Polytechnical University, Xian 710072, China
年:2010
通讯作者:Huang, X.-P.(huangxp@nwpu.edu.cn)
会议名称:2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
页码范围:533-535
会议地点:Shanghai, China
会议开始日期:2010-11-01
会议结束日期:2010-11-04
收录情况:EI(20110413609276)  
所属部门:计算机学院
人气指数:2352
浏览次数:2334
语言:外文
摘要:The tag sorting circuit in Weighted Fair Queuing (WFQ) is crucial to the Quality of Service (QoS). In this paper, we present a kind of optimized hardware architecture for fast tag sorting, which consists of one-hot encoding and leading zero counting. The architecture is parallel and pipelining. It is implemented using FPGA technology. In comparison with the traditional comparator-tree-based architecture, it can improve the frequency by 15% and reduce the area by 22%. ?2010 IEEE.
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